The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 2017
Filed:
Jun. 03, 2015
Applicant:
Globalfoundries, Inc., Grand Cayman, KY;
Inventors:
Sunil Kumar Singh, Mechanicville, NY (US);
Ravi Prakash Srivastava, Clifton Park, NY (US);
Xusheng Wu, Ballston Lake, NY (US);
Akshey Sehgal, Malta, NY (US);
Teck Jung Tang, Ballston Lake, NY (US);
Assignee:
GLOBALFOUNDRIES, INC., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/532 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/02118 (2013.01); H01L 21/02167 (2013.01); H01L 21/02282 (2013.01); H01L 21/31144 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76807 (2013.01); H01L 21/76811 (2013.01); H01L 21/76826 (2013.01); H01L 21/76843 (2013.01); H01L 21/76871 (2013.01); H01L 21/76877 (2013.01); H01L 23/53295 (2013.01);
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes depositing an organic dielectric material overlying a semiconductor substrate for forming an organic interlayer dielectric (OILD) layer. An opening is formed in the OILD layer and a conductive metal fill is deposited in the opening for forming a metal line and/or a via.