The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 14, 2017

Filed:

Sep. 16, 2013
Applicant:

Realtek Semiconductor Corp., HsinChu, TW;

Inventors:

Ming-Chung Wu, Yilan County, TW;

Shuo-Fen Kuo, Hsinchu County, TW;

Ying-Yen Chen, Chiayi County, TW;

Jih-Nung Lee, Hsinchu County, TW;

Ching-Feng Su, Hsinchu County, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 31/3193 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31937 (2013.01); G01R 31/318583 (2013.01); G06F 17/5045 (2013.01); G06F 17/505 (2013.01); G06F 17/5022 (2013.01); G06F 2217/14 (2013.01);
Abstract

A method for deciding a scan clock domain allocation of an integrated circuit includes: utilizing a circuit netlist file and a timing constraints file of the integrated circuit to find out the amount of crossing paths between any two function clock domains of a plurality of function clock domains, and generate a clock domain report file; and grouping the plurality of function clock domains and allocating the plurality of function clock domains after being grouped into a plurality of scan clock domains according to the clock domain report file.


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