The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 14, 2017
Filed:
Sep. 16, 2015
Freescale Semiconductor, Inc., Austin, TX (US);
Sagar Kataria, Noida, IN;
Anurag Jindal, Patiala, IN;
Abhishek Mahajan, Chandigarh, IN;
Mayank Parasrampuria, Jaipur, IN;
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
An integrated circuit (IC), operable in internal and external testing modes (INTEST and EXTEST), includes first and second partitions and a functional path therebetween. The first partition includes a first scan chain, a first multiplexer, and a first flip-flop. The second partition includes a second flip-flop and a second scan chain. The first scan chain generates an EXTEST vector initialization signal, based on an EXTEST scan input signal. The first multiplexer receives an INTEST vector initialization signal and the EXTEST vector initialization signal, and generates a scan input signal. The first flip-flop generates a first output signal based on the scan input signal. The functional path provides a second output signal based on the first output signal. The second flip-flop generates a third output signal based on the second output signal. The second scan chain receives the third output signal and generates a test output signal.