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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9564444 B1

PDFFull Text
Date of Patent:
Feb. 07, 2017

Filed:

Oct. 03, 2015

Method of forming integrated fin and strap structure for an access transistor of a trench capacitor

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kevin K. Chan, Staten Island, NY (US);

Babar A. Khan, Ossining, NY (US);

Dae-Gyu Park, Poughquaq, NY (US);

Xinhui Wang, Poughkeepsie, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Scully, Scott, Murphy & Presser, P.C.

Steven J. Meyers

Primary Examiner:

Eduardo A Rodela

Assistant Examiner:

Christopher M Roland

Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10867 (2013.01); H01L 27/1085 (2013.01); H01L 27/10829 (2013.01); H01L 27/10855 (2013.01); H01L 27/10861 (2013.01); H01L 27/10879 (2013.01); H01L 27/1211 (2013.01); H01L 28/40 (2013.01); H01L 29/04 (2013.01); H01L 29/0657 (2013.01); H01L 29/1033 (2013.01); H01L 29/66181 (2013.01); H01L 29/66795 (2013.01); H01L 29/945 (2013.01);
Abstract

At least one dielectric pad layer is formed on a semiconductor-on-insulator (SOI) substrate. A deep trench is formed in the SOI substrate, and a combination of an outer electrode, a node dielectric, and an inner electrode are formed such that the top surface of the inner electrode is recessed below the top surface of a buried insulator layer of the SOI substrate. Selective epitaxy is performed to fill a cavity overlying the inner electrode with an epitaxial semiconductor material portion. A top semiconductor material layer and the epitaxial semiconductor material portion are patterned to form a fin structure including a portion of the top semiconductor material layer and a portion of the epitaxial semiconductor material portion. The epitaxial semiconductor material portion functions as a conductive strap structure between the inner electrode and a semiconductor device to be formed on the fin structure.

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