The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2017
Filed:
Sep. 26, 2014
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Hsiang-Lun Kao, Taoyuan, TW;
Tien-Lu Lin, Hsin-Chu, TW;
Yung-Chih Wang, Taoyuan, TW;
Yu-Chieh Liao, Taoyuan, TW;
Assignee:
Taiwan Semiconductor Manufucturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/7685 (2013.01); H01L 21/76819 (2013.01); H01L 21/76831 (2013.01); H01L 21/76892 (2013.01); H01L 23/5222 (2013.01); H01L 23/53295 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.