The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 07, 2017
Filed:
Dec. 03, 2013
Boe Technology Group Co., Ltd., Beijing, CN;
Chengdu Boe Optoelectronics Technology Co., Ltd., Chengdu, Sichuan, CN;
Byung Chun Lee, Beijing, CN;
Donghua Jiang, Beijing, CN;
Yongyi Fu, Beijing, CN;
Wuyang Zhao, Beijing, CN;
Chundong Li, Beijing, CN;
BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;
CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Chengdu, Sichuan, CN;
Abstract
The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.