The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 2017
Filed:
Apr. 16, 2012
Chin-cheng Chien, Tainan, TW;
Chun-yuan Wu, Yun-Lin County, TW;
Chih-chien Liu, Taipei, TW;
Chin-fu Lin, Tainan, TW;
Chia-lin Hsu, Tainan, TW;
Chin-Cheng Chien, Tainan, TW;
Chun-Yuan Wu, Yun-Lin County, TW;
Chih-Chien Liu, Taipei, TW;
Chin-Fu Lin, Tainan, TW;
Chia-Lin Hsu, Tainan, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
The present invention provides a non-planar FET which includes a substrate, a fin structure, a gate and a gate dielectric layer. The fin structure is disposed on the substrate. The fin structure includes a first portion adjacent to the substrate wherein the first portion shrinks towards a side of the substrate. The gate is disposed on the fin structure. The gate dielectric layer is disposed between the fin structure and the gate. The present invention further provides a method of manufacturing the non-planar FET.