The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9559176 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 31, 2017

Filed:

Jun. 13, 2016
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Peijie Feng, Clifton Park, NY (US);

Yanxiang Liu, Glenville, NY (US);

Shesh Mani Pandey, Clifton Park, NY (US);

Jianwei Peng, Ballston Lake, NY (US);

Francis Benistant, Singapore, SG;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/45 (2006.01); H01L 27/092 (2006.01); H01L 21/285 (2006.01); H01L 21/324 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41791 (2013.01); H01L 21/28512 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/45 (2013.01); H01L 29/785 (2013.01); H01L 21/324 (2013.01); H01L 21/823431 (2013.01);
Abstract

A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.


Find Patent Forward Citations

Feng, Peijie. (2017). Finfet conformal junction and abrupt junction with reduced damage method and device (U.S. Patent No. 9559176). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9559176

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