The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 2017

Filed:

May. 19, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Bo-Ting Chen, Fengyuan, TW;

Han-Jen Yang, Taipei, TW;

Li-Wei Chu, Hsinchu, TW;

Wun-Jie Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/02 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0285 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823878 (2013.01); H01L 21/823885 (2013.01); H01L 27/0248 (2013.01); H01L 27/092 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/0676 (2013.01); H01L 29/42392 (2013.01); H01L 29/45 (2013.01); H01L 29/78618 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01);
Abstract

A semiconductor device is provided. The semiconductor device includes a first transistor on a first side of a shallow trench isolation (STI) region and a second transistor on a second side of the STI region. The first transistor includes a first conductive portion having a second conductivity type formed within a well having a first conductivity type, a first nanowire connected to the first conductive portion and a first active area, and a first gate surrounding the first nanowire. The second transistor includes a second conductive portion having the second conductivity type formed within the well, a second nanowire connected to the second conductive portion and a second active area, and a second gate surrounding the second nanowire. Excess current from an ESD event travels through the first conductive portion through the well to the second conductive portion bypassing the first nanowire and the second nanowire.


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