The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2017
Filed:
Jun. 10, 2015
Applicant:
Macronix International Co. Ltd., Hsin-chu, TW;
Inventors:
Assignee:
Macronix International Co., Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
H01L 23/528 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 21/76892 (2013.01); H01L 27/11293 (2013.01);
Abstract
Provided are improved semiconductor memory devices and methods for manufacturing such semiconductor memory devices. A method may incorporate the patterning of the array and periphery regions in self-aligned quadruple patterning and provide semiconductor devices resulting from the combined patterning.
Hung, Yu-Min. (2017). Method of manufacturing semiconductor devices with combined array and periphery patterning in self-aligned quadruple patterning (U.S. Patent No. 9553047). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9553047
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile