The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Mar. 19, 2014
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Ruilong Xie, Niskayuna, NY (US);

Ryan Ryoung-Han Kim, Albany, NY (US);

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 23/485 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 21/76877 (2013.01); H01L 21/76885 (2013.01); H01L 21/76895 (2013.01); H01L 23/485 (2013.01); H01L 27/088 (2013.01); H01L 29/665 (2013.01); H01L 21/76807 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.


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