The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 24, 2017

Filed:

Jan. 08, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Taehyun Kim, San Diego, CA (US);

Sungryul Kim, San Diego, CA (US);

Jung Pill Kim, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/07 (2006.01); H03M 13/05 (2006.01); G06F 11/10 (2006.01); G11C 29/00 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0766 (2013.01); G06F 11/1008 (2013.01); G11C 29/808 (2013.01); G11C 29/814 (2013.01); H03M 13/05 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Systems and methods for correcting bit failures in a resistive memory device include dividing the memory device into a first memory bank and a second memory bank. A first single bit repair (SBR) array is stored in the second memory bank, wherein the first SBR array is configured to store a first indication of a failure in a first failed bit in a first row of the first memory bank. The first memory bank and the first SBR array are configured to be accessed in parallel during a memory access operation. Similarly, a second SBR array stored in the first memory bank can store indications of failures of bits in the second memory bank, wherein the second SBR array and the second memory bank can be accessed in parallel. Thus, bit failures in the first and second memory banks can be corrected in real time.


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