The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

Nov. 19, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Cheong Min Hong, Austin, TX (US);

Konstantin V. Loiko, Austin, TX (US);

Juanyi Yin, Austin, TX (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/115 (2006.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/28282 (2013.01); H01L 27/11573 (2013.01); H01L 29/42344 (2013.01); H01L 29/42348 (2013.01);
Abstract

A method for forming a semiconductor device includes forming a select gate over a substrate and forming a charge storage layer and a control gate over the select gate. The charge storage layer and control gate overlap a first sidewall of the select gate and the charge storage layer is between the select gate and the control gate. A protective spacer is formed, wherein the protective spacer has a first portion adjacent a first sidewall of the charge storage layer and on the substrate, and the protective spacer is thinned. After thinning the protective spacer, a sidewall spacer is formed over the protective spacer, wherein the sidewall spacer has a first portion on the substrate, and the first portion of the protective spacer is between the first sidewall of the control gate and the first portion of the sidewall spacer.


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