The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2017
Filed:
Jun. 29, 2015
Applicant:
Tessera, Inc., San Jose, CA (US);
Inventors:
Andrey Grinman, Jerusalem, IL;
David Ovrutsky, San Jose, CA (US);
Charles Rosenstein, Ramat Beit Shemesh, IL;
Vage Oganesian, Sunnyvale, CA (US);
Assignee:
Tessera, Inc., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/50 (2006.01); H01L 23/31 (2006.01); H01L 23/556 (2006.01); H01L 25/10 (2006.01); H01L 23/29 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 23/29 (2013.01); H01L 23/3114 (2013.01); H01L 23/3135 (2013.01); H01L 23/49816 (2013.01); H01L 23/556 (2013.01); H01L 24/17 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 23/4985 (2013.01); H01L 23/49827 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/274 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1064 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/01327 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/3025 (2013.01);
Abstract
A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.