The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

Feb. 18, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ching-Fang Yu, Hsinchu, TW;

Chia-Ching Huang, Yilan County, TW;

Ting-Hao Hsu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B44C 1/22 (2006.01); C03C 15/00 (2006.01); C03C 25/68 (2006.01); C23F 1/00 (2006.01); H01L 21/308 (2006.01); H01L 21/263 (2006.01); G03F 7/20 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); G03F 7/203 (2013.01); G03F 7/70433 (2013.01); G03F 7/70466 (2013.01); H01L 21/2633 (2013.01); H01L 21/3088 (2013.01); H01L 21/0274 (2013.01);
Abstract

Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.


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