The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

Sep. 02, 2014
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Ying-Tsai Ting, Hsinchu, TW;

Che-Chin Wu, Hsinchu, TW;

Tsung-Yi Chou, Jhubei, TW;

Shih-Fu Huang, Zhongli, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/38 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 17/00 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/702 (2013.01); G11C 17/00 (2013.01); G11C 2029/1204 (2013.01);
Abstract

A test method tests a memory device including a memory array having a plurality of symmetric memory cells, a plurality of word lines and a plurality of bit lines. In testing a first word line, a first bit line is charged to test a single bit of a first half of an adjacent first symmetric memory cell; and a second bit line is charged to test a single bit of a second half of an adjacent second symmetric memory cell. In testing a second word line, the first bit line is charged to test a single bit of the second half of an adjacent third symmetric memory cell; and the second bit line is charged to test a single bit of the first half of an adjacent fourth symmetric memory cell. In testing each of the word lines, each of the bit lines is charged once.


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