The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 17, 2017

Filed:

Aug. 07, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Byeong-In Choe, Yongin-si, KR;

Jaehoon Jang, Seongnam-si, KR;

Kihyun Kim, Hwaseong-si, KR;

Sunil Shim, Seoul, KR;

Woonkyung Lee, Seongnam-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); G11C 7/00 (2006.01); H01L 29/00 (2006.01); H01L 27/11 (2006.01); G11C 16/14 (2006.01); G11C 7/14 (2006.01); G11C 16/04 (2006.01); G11C 16/30 (2006.01); H01L 29/792 (2006.01); H01L 27/115 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 7/14 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); H01L 27/11582 (2013.01); H01L 29/7926 (2013.01); G11C 16/16 (2013.01);
Abstract

A nonvolatile memory device includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of memory cells stacked in a direction perpendicular to the substrate. The methods may include applying a word line erase voltage to word lines connected to memory cells of the cell strings; floating ground selection lines connected to ground selection transistors of the cell strings and string selection lines connected to string selection transistors of the plurality of cell strings; applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings; applying an erase voltage to the substrate; and floating the at least one lower dummy word line after applying of the erase voltage.


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