The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 2017
Filed:
Mar. 09, 2016
Applicant:
Invensas Corporation, San Jose, CA (US);
Inventors:
David Edward Fisch, Pleasanton, CA (US);
William C. Plants, Campbell, CA (US);
Kent Stalnaker, Colorado Springs, CO (US);
Assignee:
Invensas Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G11C 11/4091 (2006.01); G11C 29/52 (2006.01); G11C 7/02 (2006.01); G11C 7/10 (2006.01); G11C 11/4096 (2006.01); G11C 7/00 (2006.01); G11C 11/408 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 7/00 (2013.01); G11C 7/02 (2013.01); G11C 7/1006 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01); G11C 29/52 (2013.01); G11C 7/062 (2013.01); G11C 7/065 (2013.01);
Abstract
A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.