The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 10, 2017
Filed:
Aug. 26, 2015
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Yi-Hui Lin, Changhua County, TW;
Keng-Jen Lin, Kaohsiung, TW;
Chun-Yao Yang, Kaohsiung, TW;
Yu-Ren Wang, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 21/3213 (2006.01); H01L 21/3215 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/26513 (2013.01); H01L 21/324 (2013.01); H01L 21/32055 (2013.01); H01L 21/32139 (2013.01); H01L 21/32155 (2013.01); H01L 29/66795 (2013.01);
Abstract
A method of forming a patterned hark mask layer includes the following steps. A semiconductor substrate is provided. An amorphous silicon layer is formed on the semiconductor substrate. An implantation process is performed on the amorphous silicon layer. An annealing treatment is performed on the amorphous silicon layer after the implantation process. A patterned hard mask layer is formed on the amorphous silicon layer after the annealing treatment.