The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Jul. 02, 2015
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chia-Lin Lu, Taoyuan, TW;

Chun-Lung Chen, Tainan, TW;

Kun-Yuan Liao, Hsin-Chu, TW;

Feng-Yi Chang, Tainan, TW;

En-Chiuan Liou, Tainan, TW;

Chia-Hsun Tseng, Tainan, TW;

Wei-Hao Huang, New Taipei, TW;

Yu-Ting Hung, Hsinchu, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/0276 (2013.01); H01L 21/31133 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76877 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer.


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