The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 2017

Filed:

Oct. 19, 2015
Applicant:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Inventor:

Loren McLaury, Hillsboro, OR (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/413 (2006.01); H04L 12/801 (2013.01); H04L 25/02 (2006.01); H04L 12/24 (2006.01); G01R 31/3185 (2006.01); H03M 1/00 (2006.01); H03M 1/34 (2006.01); G11C 16/24 (2006.01); G11C 17/16 (2006.01); H01L 23/498 (2006.01); H01L 23/50 (2006.01); H01L 23/60 (2006.01);
U.S. Cl.
CPC ...
G11C 11/413 (2013.01); G01R 31/318597 (2013.01); G11C 16/24 (2013.01); G11C 17/16 (2013.01); H01L 23/49838 (2013.01); H03M 1/001 (2013.01); H03M 1/34 (2013.01); H04L 25/0262 (2013.01); H04L 41/0806 (2013.01); H04L 47/10 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/50 (2013.01); H01L 23/60 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15311 (2013.01);
Abstract

In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit tracks access-device leakage current over different process, voltage, and temperature (PVT) conditions to generate a leakage-current reference voltage that drives a different leakage-current abatement device connected to each different bit-line to inject currents into the bit-lines to compensate for the corresponding leakage currents. In one implementation, the leakage-current reference circuit has a device that mimics the leakage of each access device configured in a current mirror that drives the resulting leakage-current reference voltage to the different leakage-current abatement devices.


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