The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 03, 2017

Filed:

Nov. 22, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Pranav Kalavade, San Jose, CA (US);

Feng Zhu, San Jose, CA (US);

Shyam Sunder Raghunathan, Sunnyvale, CA (US);

Ravi H. Motwani, San Diego, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G11C 29/00 (2006.01); G06F 11/07 (2006.01); G11B 20/18 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0751 (2013.01); G06F 11/073 (2013.01); G11B 20/1816 (2013.01);
Abstract

Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.


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