The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Aug. 05, 2015
Applicant:

Adesto Technologies Corporation, Sunnyvale, CA (US);

Inventors:

John Dinh, Dublin, CA (US);

Venkatesh P. Gopinath, Fremont, CA (US);

Nathan Gonzales, San Jose, CA (US);

Derric Lewis, Sunnyvale, CA (US);

Deepak Kamalanathan, Santa Clara, CA (US);

Ming Sang Kwan, San Leandro, CA (US);

Assignee:

Adesto Technologies Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 13/004 (2013.01); H01L 27/2436 (2013.01); H01L 45/12 (2013.01); H01L 45/122 (2013.01); H01L 45/1253 (2013.01); G11C 13/0011 (2013.01); G11C 13/0097 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0078 (2013.01);
Abstract

In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line; (iii) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and (iv) a diode having a cathode at the second diffusion region, and an anode at the third diffusion region, where the diode is turned on during an erase operation on the programmable impedance element.


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