The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 27, 2016

Filed:

Dec. 17, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuoyuan (Peter) Hsu, San Jose, CA (US);

Yukit Tang, Sunnyvale, CA (US);

Derek Tao, Fremont, CA (US);

Young Seog Kim, Pleasanton, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/413 (2006.01); G11C 11/419 (2006.01); G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/00 (2013.01); G11C 11/413 (2013.01);
Abstract

A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.


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