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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9525076 B1

PDFFull Text
Date of Patent:
Dec. 20, 2016

Filed:

Aug. 06, 2013

Memory device using graphene as charge-trap layer and method of operating the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Jae-ho Lee, Seoul, KR;

Hyun-jong Chung, Hwaseong-si, KR;

Seong-jun Park, Seoul, KR;

Kyung-eun Byun, Uijeongbu-si, KR;

David Seo, Yongin-si, KR;

Hyun-jae Song, Hwaseong-si, KR;

Jin-seong Heo, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do, KR;

Attorney:
Primary Examiner:

Zandra Smith

Assistant Examiner:

Lauren R Bell

Int. Cl.
CPC ...
H01L 29/792 (2006.01); B82Y 10/00 (2011.01); H01L 21/28 (2006.01); H01L 29/47 (2006.01); H01L 29/788 (2006.01); H01L 29/16 (2006.01); G11C 11/40 (2006.01); H01L 29/778 (2006.01); G11C 16/04 (2006.01); H01L 51/05 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); B82Y 10/00 (2013.01); G11C 11/40 (2013.01); G11C 16/0466 (2013.01); H01L 21/28273 (2013.01); H01L 29/1606 (2013.01); H01L 29/47 (2013.01); H01L 29/7781 (2013.01); H01L 29/788 (2013.01); H01L 51/0512 (2013.01); Y10S 977/734 (2013.01); Y10S 977/938 (2013.01);
Abstract

A graphene memory includes a source and a drain spaced apart from each other on a conductive semiconductor substrate, a graphene layer contacting the conductive semiconductor substrate and spaced apart from and between the source and the drain, and a gate electrode on the graphene layer. A Schottky barrier is formed between the conductive semiconductor substrate and the graphene layer such that the graphene layer is used as a charge-trap layer for storing charges.

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