The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 20, 2016

Filed:

Jul. 21, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Chen Su, Hualien, TW;

Huang-Ming Chen, Hsin-Chu, TW;

Chun-Feng Nieh, Hsin-Chu, TW;

Pei-Chao Su, Zhudong Town, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/092 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/3115 (2006.01); H01L 21/768 (2006.01); H01L 29/51 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0638 (2013.01); H01L 21/225 (2013.01); H01L 21/26586 (2013.01); H01L 21/31155 (2013.01); H01L 21/76825 (2013.01); H01L 21/76826 (2013.01); H01L 21/76828 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01); H01L 27/092 (2013.01); H01L 29/66545 (2013.01); H01L 29/66606 (2013.01); H01L 29/66636 (2013.01); H01L 29/7833 (2013.01); H01L 29/7834 (2013.01); H01L 29/165 (2013.01); H01L 29/517 (2013.01);
Abstract

An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.


Find Patent Forward Citations

Loading…