The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2016
Filed:
Jul. 23, 2014
Globalfoundries Singapore Pte. Ltd., Singapore, SG;
Laiqiang Luo, Singapore, SG;
Xinshu Cai, Singapore, SG;
Danny Shum, Singapore, SG;
Fan Zhang, Singapore, SG;
Khee Yong Lim, Singapore, SG;
Juan Boon Tan, Singapore, SG;
Shaoqiang Zhang, Singapore, SG;
GLOBALFOUNDRIES SINGAPORE PTE. LTD., Singapore, SG;
Abstract
A capacitor and method of forming a capacitor are presented. The capacitor includes a substrate having a capacitor region in which the capacitor is disposed. The capacitor includes first, second and third sub-capacitors (C, Cand C). The Ccomprises a metal oxide semiconductor (MOS) capacitor which includes a gate on the substrate. The gate includes a gate electrode over a gate dielectric. A first Cplate is served by the gate electrode, a second Cplate is served by the substrate of the capacitor region and a Ccapacitor dielectric is served by the gate dielectric. The Cincludes a back-end-of-line (BEOL) vertical capacitor disposed in ILD layers with metal levels and via levels. A plurality of metal lines are disposed in the metal levels. The metal lines of a metal level are grouped in alternating first and second groups, the first group serves as first Cplates and second group serves as second Cplates and the dielectric layers between the first and second groups serve as Ccapacitor dielectrics. The Cincludes a first Cplate served by the gate electrode, a second Cplate served by second group lines in the first metal level of the ILD layers, and a Ccapacitor dielectric is served by the first via level dielectric below Mand above the gate electrode. A first capacitor terminal is coupled to first capacitor plates of C, Cand Cand a second capacitor terminal is coupled to second capacitor plates of C, Cand C