The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2016

Filed:

Oct. 27, 2014
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Benfu Lin, Singapore, SG;

Wanbing Yi, Singapore, SG;

Wei Lu, Singapore, SG;

Alex See, Singapore, SG;

Juan Boon Tan, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/3105 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 21/31051 (2013.01); H01L 21/76807 (2013.01); H01L 21/76877 (2013.01); H01L 23/3192 (2013.01); H01L 23/53295 (2013.01); H01L 24/03 (2013.01); H01L 23/3114 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05573 (2013.01); H01L 2924/06 (2013.01); H01L 2924/07025 (2013.01);
Abstract

Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.


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