The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2016
Filed:
Dec. 19, 2013
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sven Albers, Regensburg, DE;
Michael Skinner, San Jose, CA (US);
Hans-Joachim Barth, Munich, DE;
Peter Baumgartner, Munich, DE;
Harald Gossner, Riemerling, DE;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/552 (2006.01); H01L 23/522 (2006.01); H01L 29/06 (2006.01); H01L 23/00 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01); H01L 23/552 (2013.01); H01L 23/562 (2013.01); H01L 23/564 (2013.01); H01L 24/17 (2013.01); H01L 24/49 (2013.01); H01L 24/81 (2013.01); H01L 24/85 (2013.01); H01L 25/065 (2013.01); H01L 27/0207 (2013.01); H01L 29/0657 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/4813 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/49 (2013.01); H01L 2224/81801 (2013.01); H01L 2224/85801 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/19104 (2013.01);
Abstract
Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.