The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 06, 2016

Filed:

Sep. 27, 2013
Applicant:

Silex Microsystems Ab, Jarfalla, SE;

Inventors:

Thorbjorn Ebefors, Huddinge, SE;

Henrik Knutsson, Vastervik, SE;

Assignee:

SILEX MICROSYSTEMS AB, Jarfalla, SE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/768 (2006.01); H01L 21/288 (2006.01); H01L 23/48 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/0217 (2013.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/288 (2013.01); H01L 21/76847 (2013.01); H01L 21/76874 (2013.01); H01L 21/76879 (2013.01); H01L 21/76888 (2013.01); H01L 21/76892 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings <10 μm are provided on both sides of the wafer.


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