The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Jan. 21, 2016
Applicant:

Mie Fujitsu Semiconductor Limited, Kuwana, Mie, JP;

Inventors:

Thomas Hoffmann, Los Gatos, CA (US);

Pushkar Ranade, Los Gatos, CA (US);

Scott E. Thompson, Gainesville, FL (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/161 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1108 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823842 (2013.01); H01L 21/823878 (2013.01); H01L 27/092 (2013.01); H01L 27/1116 (2013.01); H01L 29/0649 (2013.01); H01L 29/1033 (2013.01); H01L 29/161 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 27/1104 (2013.01);
Abstract

A semiconductor device includes a substrate having a semiconducting surface having formed therein a first active region and a second active region, where the first active region consists of a substantially undoped layer at the surface and a highly doped screening layer of a first conductivity type beneath the first substantially undoped layer, and the second active region consists of a second substantially undoped layer at the surface and a second highly doped screening layer of a second conductivity type beneath the second substantially undoped layer. The semiconductor device also includes a gate stack formed in each of the first active region and the second active region consists of at least one gate dielectric layer and a layer of a metal, where the metal has a workfunction that is substantially midgap with respect to the semiconducting surface.


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