The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2016

Filed:

Sep. 14, 2015
Applicants:

Hong-bae Park, Seoul, KR;

Ja-hum Ku, Seoul, KR;

Myeong-cheol Kim, Suwon-si, KR;

Jin-wook Lee, Seoul, KR;

Sung-kee Han, Seoul, KR;

Inventors:

Hong-bae Park, Seoul, KR;

Ja-hum Ku, Seoul, KR;

Myeong-cheol Kim, Suwon-si, KR;

Jin-wook Lee, Seoul, KR;

Sung-kee Han, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 27/11 (2006.01); H01L 27/092 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 27/0207 (2013.01); H01L 27/0924 (2013.01);
Abstract

A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.


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