The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Jan. 04, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-chu, TW;

Inventors:

Ying-Yu Hsu, Hsinchu, TW;

Ruey-Bin Sheen, Hsinchu, TW;

Chih-Hsien Chang, New Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/02 (2006.01); H03K 3/012 (2006.01); H01L 25/065 (2006.01); G01R 31/26 (2014.01); G01R 31/30 (2006.01); G01R 31/319 (2006.01); G01R 31/3193 (2006.01); H03K 17/94 (2006.01); H03K 3/017 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); G01R 31/26 (2013.01); G01R 31/2607 (2013.01); G01R 31/3004 (2013.01); G01R 31/3191 (2013.01); G01R 31/3193 (2013.01); G01R 31/31924 (2013.01); H01L 25/0657 (2013.01); H03K 3/017 (2013.01); H03K 17/94 (2013.01); H01L 25/18 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3D architecture/stack for adaptively calibrating a chip in a 3D architecture/stack. In one embodiment, the system includes a first chip and a second chip located within the 3D chip stack, wherein the first chip generates a calibration signal, the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal, that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal.


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