The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2016
Filed:
May. 28, 2014
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Ting-Chang Chang, Kaohsiung, TW;
Kuan-Chang Chang, Kaohsiung, TW;
Tsung-Ming Tsai, Kaohsiung, TW;
Chih-Hung Pan, Taichung, TW;
Ying-Lang Wang, Tai-Chung, TW;
Kei-Wei Chen, Tainan, TW;
Shih-Chieh Chang, Taipei, TW;
Te-Ming Kung, Taichung, TW;
Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;
Abstract
A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous silicon oxide or porous hafnium oxide. The group-IV element may comprise zirconium, titanium, or hafnium. The porous low-k layer may be prepared by inductively coupled plasma (ICP) treatment. A method of fabricating a resistive memory is disclosed. The method comprises forming a resistance-switching network on a first electrode using sputtering and forming a second electrode on the resistance-switching network using sputtering. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer.