The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 22, 2016

Filed:

Dec. 18, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Tsung-Yao Wen, Hsin-Chu, TW;

Sai-Hooi Yeong, Hsin-Chu, TW;

Sheng-Chen Wang, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66818 (2013.01); H01L 27/0886 (2013.01);
Abstract

A FinFET having fin back biasing and methods of forming the same are disclosed. The FinFET includes a substrate and a fin over the substrate. The fin includes a source region, a drain region, a channel region, and a biasing region. The source and drain regions sandwich the channel region. The channel region and the biasing region sandwich one of the source and drain regions. The FinFET further includes a gate over the substrate. The gate engages the fin adjacent to the channel region, thereby forming a field effect transistor (FET). The biasing region is configured to bias the FET body effect when a voltage is applied to the biasing region. From a cross sectional view, the source region and the biasing region each have a substantially rectangular profile, wherein the source region is taller and wider than the biasing region.


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