Non-volatile semiconductor storage device

Abstract

Provided is a non-volatile semiconductor memory device capable of reliably preventing a malfunction of a read transistor without increasing the number of bit lines. In a non-volatile semi conductor memory device (), program transistors () and erase transistors () serving as charge transfer paths during data programming and erasure are provided while a second bit line (BLN) connected to the program transistor () in a first cell () for performing data programming also serves as a reading bit line in the other second cell () by switching switch transistors (SWa, SWb) so that malfunctions of read transistors () that occur because the read transistors are used for data programming and erasure can be reliably prevented without the number of bit lines being increased.