The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 15, 2016

Filed:

Jan. 20, 2016
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Man-Tang Wu, Hsinchu County, TW;

Jeng-Wei Yang, Zhubei, TW;

Chien-Sheng Su, Saratoga, CA (US);

Chun-Ming Chen, Taipei, TW;

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66537 (2013.01); H01L 27/11519 (2013.01); H01L 27/11546 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01);
Abstract

A method of forming a memory device on a substrate having memory, LV and HV areas, including forming pairs of spaced apart memory stacks in the memory area, forming a first conductive layer over and insulated from the substrate, forming a first insulation layer on the first conductive layer and removing it from the memory and HV areas, performing a conductive material deposition to thicken the first conductive layer in the memory and HV areas, and to form a second conductive layer on the first insulation layer in the LV area, performing an etch to thin the first conductive layer in the memory and HV areas and to remove the second conductive layer in the LV area, removing the first insulation layer from the LV area, and patterning the first conductive layer to form blocks of the first conductive layer in the memory, LV and HV areas.


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