The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2016

Filed:

Mar. 10, 2015
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Kuo-Pin Chang, Yuanli Township, Miaoli County, TW;

Hang-Ting Lue, Hsinchu, TW;

Wen-Wei Yeh, Bade, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0466 (2013.01); G11C 16/0475 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01);
Abstract

A method is provided for operating a NAND array that includes a plurality of blocks of memory cells. A block of memory cells includes a plurality of NAND strings having channel lines between first string select switches and second string select switches. The plurality of NAND strings shares a set of word lines between the first and second string select switches. A channel-side erase voltage is applied to the channel lines through the first string select switches in a selected block. Word line-side erase voltages are applied to a selected subset of the set of word lines in the selected block to induce tunneling in memory cells coupled to the selected subset. Word line-side inhibit voltages are applied to an unselected subset of the set of word lines in the selected block to inhibit tunneling in memory cells coupled to the unselected subset.


Find Patent Forward Citations

Loading…