The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

May. 30, 2014
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;

Inventors:

Jeng-Chang Her, Tainan, TW;

Chia-Cheng Lin, Taipei, TW;

Hung-Jui Chang, Shetou Shiang, TW;

Yu-Sheng Su, Tainan, TW;

Shu-Huei Suen, Jhudong Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28518 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01); H01L 21/76897 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a wafer having a central portion and a peripheral portion surrounding the central portion. The method includes forming a first dielectric layer over the central portion. The first dielectric layer has first contact openings exposing conductive regions of the wafer. The method includes forming a protective layer over the peripheral portion. The method includes after forming the protective layer, performing a metal silicide process to form metal silicide structures over the conductive regions of the wafer.


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