The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2016

Filed:

Apr. 09, 2013
Applicant:

Elite Semiconductor Memory Technology Inc., Hsinchu, TW;

Inventor:

Jen-Shou Hsu, Hsinchu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/56 (2006.01); G11C 29/14 (2006.01); G11C 29/40 (2006.01); G11C 29/48 (2006.01); G11C 29/50 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G11C 29/56 (2013.01); G11C 29/14 (2013.01); G11C 29/40 (2013.01); G11C 29/48 (2013.01); G11C 29/1201 (2013.01); G11C 29/50 (2013.01);
Abstract

A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable.


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