The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 25, 2016
Filed:
May. 20, 2015
Applicant:
Globalfoundries Inc., Grand Cayman, KY;
Inventors:
Kangguo Cheng, Albany, NY (US);
Bruce B. Doris, Albany, NY (US);
Ali Khakifirooz, Los Altos, NY (US);
Pranita Kulkarni, Albany, NY (US);
Ghavam G. Shahidi, Yorktown Heights, NY (US);
Assignee:
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/76 (2006.01); H01L 31/036 (2006.01); H01L 31/112 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7847 (2013.01); H01L 29/7841 (2013.01); H01L 21/02532 (2013.01); H01L 21/02664 (2013.01); H01L 21/26506 (2013.01); H01L 29/785 (2013.01);
Abstract
A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.