The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Feb. 19, 2014
Applicant:

Power Integrations, Inc., San Jose, CA (US);

Inventors:

Vijay Parthasarathy, Sunnyvale, CA (US);

Sujit Banerjee, San Jose, CA (US);

Wayne B. Grabowski, Los Altos, CA (US);

Assignee:

Power Integrations, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 29/407 (2013.01); H01L 21/76224 (2013.01);
Abstract

A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.


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