The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Feb. 08, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ding-Yuan Chen, Taichung, TW;

Chen-Hua Yu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/10 (2006.01); H01L 29/165 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 21/823857 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/66628 (2013.01); H01L 29/66636 (2013.01); H01L 29/7833 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method for forming a semiconductor structure includes providing a semiconductor substrate including a first region and a second region; and forming a first and a second metal-oxide-semiconductor (MOS) device. The step of forming the first MOS device includes forming a first silicon germanium layer over the first region of the semiconductor substrate; forming a silicon layer over the first silicon germanium layer; forming a first gate dielectric layer over the silicon layer; and patterning the first gate dielectric layer to form a first gate dielectric. The step of forming the second MOS device includes forming a second silicon germanium layer over the second region of the semiconductor substrate; forming a second gate dielectric layer over the second silicon germanium layer with no substantially pure silicon layer therebetween; and patterning the second gate dielectric layer to form a second gate dielectric.


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