The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Sep. 10, 2015
Applicant:

Alpha and Omega Semiconductor Incorporated, Sunnyvale, CA (US);

Inventors:

Yan Xun Xue, Los Gatos, CA (US);

Hamza Yilmaz, Saratoga, CA (US);

Yueh-Se Ho, Sunnyvale, CA (US);

Jun Lu, San Jose, CA (US);

Ming-Chen Lu, Shanghai, CN;

Hongtao Gao, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 23/492 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49517 (2013.01); H01L 23/492 (2013.01); H01L 23/49541 (2013.01); H01L 23/49551 (2013.01); H01L 23/49575 (2013.01); H01L 24/40 (2013.01); H01L 23/49537 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/40139 (2013.01); H01L 2224/40245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.


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