The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 18, 2016
Filed:
Aug. 18, 2015
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4076 (2006.01); G11C 8/12 (2006.01); G11C 8/10 (2006.01); G11C 11/4096 (2006.01); G11C 11/4063 (2006.01); G11C 11/4097 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G11C 8/10 (2013.01); G11C 8/12 (2013.01); G11C 11/408 (2013.01); G11C 11/4063 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01); G11C 11/4097 (2013.01); G11C 2207/005 (2013.01); G11C 2207/2209 (2013.01);
Abstract
Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.