The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 18, 2016

Filed:

Dec. 20, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rajesh M. Sankaran, Portland, OR (US);

Neil M. Schaper, Folsom, CA (US);

Joseph Nuzman, Haifa, IL;

Larisa Novakovsky, Haifa, IL;

Yen-Cheng Liu, Portland, OR (US);

Gilbert Neiger, Portland, OR (US);

Raj K. Ramanujan, Federal Way, WA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/0804 (2013.01); G06F 12/0815 (2013.01); G06F 12/0831 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/222 (2013.01);
Abstract

An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.


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