The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 11, 2016

Filed:

Jan. 22, 2015
Applicant:

Faraday Technology Corporation, Hsinchu, TW;

Inventors:

Ching-Te Chuang, Hsinchu, TW;

Chien-Yu Lu, Hsinchu, TW;

Ming-Ching Zheng, Hsinchu, TW;

Ming-Hsien Tu, Hsinchu, TW;

Assignee:

Faraday Technology Corp., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); G11C 8/16 (2006.01); G11C 11/412 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 8/16 (2013.01); G11C 11/412 (2013.01);
Abstract

A circuit for mitigating write disturbance including a first and a second discharge control paths is provided and applied to the dual-port SRAM. The first discharge control path is connected to bit lines of the second port and the first port, and a first control line. The second discharge control path is connected to inverse bit lines of the second port and the first port, and the first control line. A first discharge current is generated when the bit line of the second and the first ports are respectively at a high level voltage, and a low level voltage, and the first control line operates. A second discharge current is generated when the inverse bit line of the second and the first ports are respectively at the high level voltage and the low level voltage, and the first control line operates.


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