Clock and data recovery circuit and clock and data recovery method

Abstract

A clock and data recovery (CDR) circuit includes a phase detector, a phase interpolator, a finite state machine, and a divisor-controllable frequency divider. The phase detector compares an input data signal with a frequency dividing signal and generates a phase indication signal to indicate a phase difference between the input data signal and the frequency dividing signal. The phase interpolator performs phase interpolation on first and second clock signals received by the phase interpolator, so as to generate a phase interpolation signal. The finite state machine coupled to the phase detector and the phase interpolator generates the control signal based on the phase indication signal and the phase interpolation signal. The divisor-controllable frequency divider coupled to the phase detector and the phase interpolator divides the second frequency of the phase interpolation signal by a divisor so as to generate the frequency dividing signal. A CDR method is also provided.