The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 04, 2016

Filed:

Dec. 26, 2013
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

David L. Peart, Round Rock, TX (US);

Yan Lin, Pleasanton, CA (US);

Aiguo Lu, San Jose, CA (US);

Balkrishna R. Rashingkar, San Jose, CA (US);

Russell B. Segal, Sunnyvale, CA (US);

Peiqing Zou, San Jose, CA (US);

Assignee:

SYNOPSYS, INC., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 2217/78 (2013.01); Y02E 60/76 (2013.01); Y04S 40/22 (2013.01);
Abstract

Embodiments are described in which shaping is integrated with power network synthesis (PNS) for power grid (PG) alignment. Specifically, some embodiments create placement constraints based on the PG that is expected to be created by PNS, and then perform shaping (or perform legalization) on the circuit design based on the placement constraints. This ensures that the physical partitions (e.g., instances of multiply-instantiated-blocks) are aligned with the power grid during shaping.


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