The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2016
Filed:
Mar. 17, 2016
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Po-Chao Tsao, New Taipei, TW;
Lung-En Kuo, Tainan, TW;
Chien-Ting Lin, Hsinchu, TW;
Shih-Fang Tzou, Tainan, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 21/308 (2006.01); H01L 21/3105 (2006.01); H01L 21/027 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/0273 (2013.01); H01L 21/3086 (2013.01); H01L 21/31053 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/0653 (2013.01); H01L 29/0657 (2013.01);
Abstract
The present invention provides a semiconductor structure including a substrate, at least one fin group and a plurality of sub-fin structures disposed on the substrate, wherein the fin group is disposed between two sub-fin structures, and a top surface of each sub-fin structure is lower than a top surface of the fin group; and a shallow trench isolation (STI) disposed in the substrate, wherein the sub-fin structures are completely covered by the shallow trench isolation.